CY28442ZXC-2【PDF 18/19 页】IC CLOCK ALVISO PENTM 56TSSOP

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Sheet目录1992

14页 15页 16页 17页 [18页]19页

CY28442-2

....................... Document #: 38-07691 Rev. *B Page 8 of 19

CLKREQ#A

SRC[T/C]2 CLKREQ#A control

1 = SRC[T/C]2 stoppable by CLKREQ#A pin

0 = SRC[T/C]2 not controlled by CLKREQ#A pin

RESERVED

Byte 9: Control Register 9

Bit

@Pup

Name

Description

96_100_SSC Spread Spectrum Selection table:

S[3:0]

SS%

‘0000’ = –0.8%(Default value)

‘0001’ = –1.0%

‘0010’ = –1.25%

‘0011’ = –1.5%

‘0100’ = –1.75%

‘0101’ = –2.0%

‘0110’ = –2.5%

‘0111’ = –0.5%

‘1000’ = ±0.25%

‘1001’ = ±0.4%

‘1010’ = ±0.5%

‘1011’ = ±0.6%

‘1100’ = ±0.8%

‘1101’ = ±1.0%

‘1110’ = ±1.25%

‘1111’ = ±1.5%

96_100 SEL

Software select 96_100_SSC output frequency, 0 = 96 MHz, 1 = 100 MHz.

96_100 Enable

96_100_SSC Enable, 0 = Disable, 1 = Enable.

96_100 SS Enable

96_100_SSC Spread spectrum enable. 0 = Disable, 1 = Enable.

96_100 SW HW

Select output frequency of 96_100_SSC via software or hardware

0 = Hardware, 1 = Software.

Byte 10: Control Register 10

Bit

@Pup

Name

Description

RESERVED

CLKREQ#B

SRC[T/C]4 CLKREQ#B control

1 = SRC[T/C]4 stoppable by CLKREQ#B pin

0 = SRC[T/C]4not controlled by CLKREQ#B pin

CLKREQ#B

SRC[T/C]2 CLKREQ#B control

1 = SRC[T/C]2 stoppable by CLKREQ#B pin

0 = SRC[T/C]2 not controlled by CLKREQ#B pin

RESERVED

CLKREQ#A

SRC[T/C]7CLKREQ#A control

1 = SRC[T/C]7 stoppable by CLKREQ#A pin

0 = SRC[T/C]7 not controlled by CLKREQ#A pin

CLKREQ#A

SRC[T/C]5 CLKREQ#A control

1 = SRC[T/C]5 stoppable by CLKREQ#A pin

0 = SRC[T/C]5 not controlled by CLKREQ#A pin

CLKREQ#A

SRC[T/C]3 CLKREQ#A control

1 = SRC[T/C]3 stoppable by CLKREQ#A pin

0 = SRC[T/C]3 not controlled by CLKREQ#A pin

CLKREQ#A

SRC[T/C]1 CLKREQ#A control

1 = SRC[T/C]1 stoppable by CLKREQ#A pin

0 = SRC[T/C]1 not controlled by CLKREQ#A pin

Byte 8: Control Register 8 (continued)

Bit

@Pup

Name

Description

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